1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to a bond pad structure capable of implementing bonding over active circuitry and reducing parasitic capacitance in an integrated circuit.
2. Description of the Prior Art
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. These advancements have been accompanied by an increased demand for faster operation, reduction in cost, and higher reliability of semiconductor devices. The ability to form structures in increasingly smaller areas having increasingly dense circuitry, as well as the ability to place more semiconductor chips on a wafer, are important for meeting these and other needs of advancing technologies.
In order to reduce the size of the chip, it is desirable to form bond pads directly over active circuitry. As known in the art, bond pads are typically arranged in rows along four chip sides. The conventional design rules exclude the area covered by the bond pads from use for laying out actual circuit patterns because of the high risk of damaging the circuit structures due to the unavoidable forces needed in the bonding process such as wire bonding process or gold ball bonding process. To implement the bonding over active circuitry, various reinforced pad structures, which are mainly used to counteract mechanical stress exerted on the pad during the bonding process, have been employed. However, such reinforced pad structures increase the parasitic capacitance in an integrated circuit, which adversely affects the chip performance.